In general, a power amplifier can be made by selecting and incorporating at least one of a bipolar transistor, a laterally double diffused metal oxide semiconductor (LDMOS) transistor, and a field effect transistor (FET), depending on desired use. The linearity, efficiency, maximum output power, and performance have improved for such devices in relation to cost. Current drift problems due to the required high power of an LDMOS transistor and the reliability of a power transistor have remarkably improved over time, making LDMOS transistors more desirable in power amplifiers.
Devices which are operable at high voltages that are close to a theoretical breakdown voltage of a semiconductor may be preferred in power semiconductor devices. Accordingly, when an external system using relatively high voltages is controlled by an integrated circuit, the integrated circuit may require a device for high voltage control which should have a structure accommodating a high breakdown voltage. For example, the drain or source of a transistor may receive a relatively high voltage from an external system. A punch through voltage between the drain and source and the semiconductor substrate and a breakdown voltage between the drain and source and a well or substrate should be higher than the relatively high voltage of the external system. Accordingly, BiCMOS power semiconductor devices in which a bipolar transistor and an LDMOS transistor are combined may be appropriately employed as a power semiconductor device.
Example FIG. 1 illustrates a structure of a BiCMOS power semiconductor device in accordance with the related art. A BiCMOS power semiconductor device may be formed on epitaxial layer 10 having a first conductive type. An LDMOS transistor may be formed on a partial region (hereinafter referred to as first region 20) in epitaxial layer 10. A bipolar transistor may be formed on another partial region (hereinafter referred to as second region 50).
First region 20 may include high-voltage well 22 of a second conductive type formed in a partial region within the epitaxial layer 10. First region 20 may include gate pattern 25 overlapping field oxide film 24. First conductive type body 28 may be formed at one side of the gate pattern 25 within high-voltage well 22 of the second conductive type and source region 30 formed within first conductive type body 28. Low-voltage well 32 of the second conductive type including drain region 34 may be formed at another side of gate pattern 25. A LDMOS transistor having an example structure illustrated in FIG. 1 may be formed at the first region 20 and may be separated from a bipolar transistor formed at second region 50, separated by the field oxide film 24.
Second region 50 may include at least one of: (1) Buried layer (NBL) 52 of the second conductive type formed within epitaxial layer 10. (2) A high-voltage well 54 of the second conductive type may be formed within the epitaxial layer 10 over buried layer 52 of the second conductive type. (3) Deep sink region 58 of the second conductive type may be connected to one side of buried layer 52 of the second conductive type and may have collector region 56. (4) First conductive type well 60 may be formed within the high-voltage well 54 of the second conductive type. (5) Base region 62 and emitter region 64 may be formed within first conductive type well 60.
Collector region 56 and emitter region 64 may be formed by implantation of second conductive type impurity ions. Base region 62 may be formed by implantation of first conductive type impurity ions.
In the BiCMOS power semiconductor device illustrated in example FIG. 1, when the LDMOS transistor is forward biased at a junction between drain region 34 and semiconductor substrate, electrons moves toward deep sink region 58 of the second conductive type connected to collector region 56. These electrons may cause noise in the bipolar transistor, thereby lowering reliability of the semiconductor device.